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| RFG60P03, RFP60P03, RF1S60P03SM Data Sheet July 1999 File Number 3951.3 60A, 30V, 0.027 Ohm, P-Channel Power MOSFETs These P-Channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49045. Features * 60A, 30V * rDS(ON) = 0.027 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER RFG60P03 RFP60P03 RF1S60P03SM PACKAGE TO-247 TO-220AB TO-263AB BRAND RFG60P03 RFP60P03 F1S60P03 Symbol D G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, i.e. RF1S60P03SM9A. S Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) JEDEC TO-220AB DRAIN (FLANGE) SOURCE DRAIN GATE JEDEC TO-263AB DRAIN (FLANGE) GATE SOURCE 4-140 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 RFG60P03, RFP60P03, RF1S60P03SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG60P03, RFP60P03, RFS60P03SM -30 -30 20 60 Refer to Peak Current Curve Figure 6 176 1.17 -55 to 175 300 260 UNITS V V V A Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage, (Rgs = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg W W/oC oC oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(-10) Qg(TH) CISS COSS CRSS RJC RJA (Figure 3) TO-220AB, TO- 263AB TO-247 VGS = 0 to -20V VGS = 0 to -10V VGS = 0 to -2V VDD = -24V, ID 60A, RL = 0.4 Ig(REF) = -3mA TEST CONDITIONS ID = 250A, VGS = 0V (Figure 11) VGS = VDS, ID = 250A (Figure 10) VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, TC = 150oC VGS = 20V ID = 60A, VGS = 10V VDD = 15V, ID 60A, RL = 0.25, VGS = -10V, RG = 2.5, (Figure 13) MIN -30 -2 TYP 20 75 35 40 190 100 7.5 3000 1500 525 MAX -4 -1 -50 100 0.027 140 115 230 120 9 0.85 62 30 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time NOTE: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) SYMBOL VSD trr TEST CONDITIONS ISD = -60A ISD = -60A, dISD/dt = 100A/s MIN TYP MAX -1.75 200 UNITS V ns 4-141 RFG60P03, RFP60P03, RF1S60P03SM Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID , DRAIN CURRENT (A) 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) Unless Otherwise Specified -70 -60 -50 -40 -30 -20 -10 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 ZJC, NORMALIZED THERMAL IMPEDANCE 0.5 PDM 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE NOTES: t1 t2 DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 t , RECTANGULAR PULSE DURATION (s) 100 101 0.01 10-5 10-4 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE -500 100s ID , DRAIN CURRENT (A) -100 1ms IDM , PEAK CURRENT (A) -103 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: 175 - T C I = I 25 ----------------------- 150 VGS = -20V 10ms -10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED -1 -1 100ms DC VGS = -10V -102 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-6 10-5 10-4 10-3 10-2 10-1 t , PULSE WIDTH (ms) 100 101 -10 VDS , DRAIN TO SOURCE VOLTAGE (V) -60 -50 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY 4-142 RFG60P03, RFP60P03, RF1S60P03SM Typical Performance Curves -200 IAS , AVALANCHE CURRENT (A) STARTING TJ = 25oC ID, DRAIN CURRENT (A) -100 -90 Unless Otherwise Specified (Continued) -120 VGS = -20V VGS = -10V VGS = -8V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = -7V -30 VGS = -4.5V 0 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 0 -1.5 -3.0 -4.5 -6.0 -7.5 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS = -6V VGS = -5V STARTING TJ = 150oC -60 If R = 0 tAV = (L) (IAS) / (1.3RATED BVDSS - VDD) If R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] -10 0.01 NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS IDS(ON), DRAIN TO SOURCE CURRENT (A) -120 25oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = -15V -55oC 2 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 1.5V, ID = 60A -90 175oC -60 1.5 1 -30 0.5 0 0 -2 -4 -6 -8 -10 0 -80 -40 0 40 80 120 160 200 VGS , GATE TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (oC) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 2 ID = 250A 1.5 1.5 1 1 0.5 0.5 0 -80 -40 0 40 80 120 160 200 0 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 4-143 RFG60P03, RFP60P03, RF1S60P03SM Typical Performance Curves 5000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS Unless Otherwise Specified (Continued) -30 VDS , DRAIN TO SOURCE VOLTAGE (V) VDD = BVDSS -22.5 RL = 0.5 IG(REF) = -3mA VGS = -10V 0.75 BVDSS 0.75 BV 0.50 BVDSS -7.5 0.25 BVDSS VDD = BVDSS -7.5 -10 VGS , GATE TO SOURCE VOLTAGE (V) 4000 C, CAPACITANCE (pF) CISS 3000 COSS 2000 -15 -5.0 DSS 0.50 BVDSS 0.25 BVDSS -2.5 1000 CRSS 0 0 -5 -10 -15 -20 -25 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 20 IG(REF) IG(ACT) t, TIME (s) 80 IG(REF) IG(ACT) 0 NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0 + VDD VDD 0V VGS DUT tP IAS 0.01 IAS tP BVDSS VDS FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORM tON td(ON) VDS RL VGS 0 tr 10% tOFF td(OFF) tf 10% VDD VGS RGS + VDS VGS 0 90% 90% DUT 10% 50% PULSE WIDTH 90% 50% FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS 4-144 RFG60P03, RFP60P03, RF1S60P03SM Test Circuits and Waveforms VDS RL 0 VGS = -2V VGS VDD + (Continued) Qg(TH) VDS -VGS Qg(-10) VDD Qg(TOT) 0 IG(REF) VGS = -10V DUT IG(REF) VGS = -20V FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS 4-145 RFG60P03, RFP60P03, RF1S60P03SM PSPICE Electrical Model .SUBCKT RFP60P03 2 1 3 CA 12 8 5.01e-9 CB 15 14 3.9e-9 CIN 6 8 3.09e-9 10 REV 6/21/94 - DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -36.59 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.92e-9 LSOURCE 3 7 2.36e-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 12 GATE 1 LGATE 9 20 RGATE 6+ 8 ESG 5 LDRAIN DRAIN 2 RDRAIN EBREAK DPLCAP 11 16 VTO EVTO + 18 8 RIN + 21 6 CIN 8 RSOURCE MOS1 MOS2 DBREAK 17 18 + DBODY - 7 LSOURCE 3 SOURCE S1A 13 8 S1B CA EGS + S2A 14 13 S2B 13 CB 6 8 + EDS 5 8 14 IT 15 17 RBREAK 18 RVTO 19 VBAT + RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1e-4 RGATE 9 20 3.25 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 11.28e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.92 - - .MODEL DBDMOD D (IS=4.21e-13 RS=1e-2 TRS1=-2.69e-4 TRS2=-1.33e-6 CJO=5.05e-9 TT=5.33e-8) .MODEL DBKMOD D (RS=3.80e-2 TRS1=-4.76e-4 TRS2=-4.17e-12) .MODEL DPLCAPMOD D (CJO=4.05e-9 IS=1e-30 N=10) .MODEL MOSMOD PMOS (VTO=-3.98 KP=16.27 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=8.05e-4 TC2=1.48e-6) .MODEL RDSMOD RES (TC1=2.80e-3 TC2=2.62e-6) .MODEL RVTOMOD RES (TC1=-3.34e-3 TC2=1.46e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=7.5 VOFF=4.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.5 VOFF=7.5) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.43 VOFF=-3.57) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.57 VOFF=1.43) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; authors, William J. Hepp and C. Frank Wheatley. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 4-146 |
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